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9db233 idt ? two output differential buffer for pcie gen3 1667c?04/20/11 two output differential buffer for pcie gen3 1 datasheet recommended application: 2 output pcie gen3 zero-delay/fanout buffer general description: the 9db233 zero-delay buffer supports pcie gen3 requirements, while being backwards compatible to pcie gen2 and gen1. the 9db233 is driven by a differential src output pair from an idt 932s421 or 932sq420 or equivalent main clock generator. it attenuates jitter on the input clock and has a selectable pll bandwidth to maximize performance in systems with or without spread-spectrum clocking. an smbus interface allows control of the pll bandwidth and bypass options, while 2 clock request (oe#) pins make the 9db233 suitable for express card applications. key specifications: ? cycle-to-cycle jitter < 50 ps ? output-to-output skew < 50 ps ? pcie gen3 phase jitter < 1.0ps rms features/benefits: ? oe# pins/suitable for express card applications ? pll or bypass mode/pll can dejitter incoming clock ? selectable pll bandwidth/minimizes jitter peaking in downstream pll's ? spread spectrum compatible/tracks spreading input clock for low emi ? smbus interface/unused outputs can be disabled output features: ? 2 - 0.7v current mode differential output pairs (hscl) block diagram spread compatible pll control logic smbdat smbclk src_in src_in# pll_bw iref dif_0 dif_1 oe1# oe0#
idt ? two output differential buffer for pcie gen3 1667c?04/20/11 9db233 two output differential buffer for pcie gen3 2 datasheet pin configuration power distribution table vdd gnd 5,9,12,16 6,15 differential outputs 9 6 smbus 20 19 iref 20 19 analog vdd & gnd for pll core description pin number pll_bw 1 20 vdda src_in 2 19 gnda src_in# 3 18 iref voe0# 4 17 voe1# vdd 5 16 vdd gnd 6 15 gnd dif_0 7 14 dif_1 dif_0# 8 13 dif_1# vdd 9 12 vdd smbd at 10 11 smbclk 9db233 note: pins preceeded by ' v ' have internal 120k ohm pull down resistors
idt ? two output differential buffer for pcie gen3 1667c?04/20/11 9db233 two output differential buffer for pcie gen3 3 datasheet pin description pin # pin name pin type description 1pll_bwin 3.3v input for selecting pll band width 0 = low, 1= hi g h 2 src_in in 0.7 v differential src true input 3 src_in# in 0.7 v differential src complementary input 4voe0# in active low input for enabling dif pair 0. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 5 vdd pwr power su pp l y , nominal 3.3v 6gnd pwr ground p in. 7 dif_0 out 0.7v differential true clock output 8 dif_0# out 0.7v differential complementary clock output 9 vdd pwr power supply, nominal 3.3v 1 0 sm bd at i/o d ata p in of smbus circuitr y , 5v tolerant 11 smbclk in clock p in of smbus circuitr y , 5v tolerant 12 vdd pwr power su pp l y , nominal 3.3v 13 dif_1# out 0.7v differential complementary clock output 14 dif_1 out 0.7v differential true clock output 15 gnd pwr ground pin. 16 vdd pwr power su pp l y , nominal 3.3v 17 voe1# in activ e lo w inp ut for enabling dif pair 1. this pin has an i ntern al pull -dow n. 1 =disable outputs, 0 = enable outputs 18 iref out this pin establishes the reference for the differential current-mode output pairs. it requires a fixed precision resistor to ground. 475ohm is the standard value for 100ohm differential impedance. other impedances require different values. see data sheet. 19 gnda pwr ground p in for the pll core. 20 vdda pwr 3.3v power for the pll core. pins preceeded by ' v ' have internal 120k ohm pull down resistors note:
idt ? two output differential buffer for pcie gen3 1667c?04/20/11 9db233 two output differential buffer for pcie gen3 4 datasheet electrical characteristics - absolute maximum ratings parameter symbol conditions min typ max units notes 3.3v core supply voltage vdda 4.6 v 1,2 3.3v logic supply voltage vdd 4.6 v 1,2 input low voltage v il gnd-0.5 v 1 input high voltage v ih except for smbus interface v dd +0.5v v 1 input high voltage v ihsmb smbus clock and data pins 5.5v v 1 storage temperature ts -65 150 c 1 junction temperature tj 125 c 1 input esd protection esd prot human body model 2000 v 1 1 guaranteed by design and characterization, not 100% tested in production. 2 operation under these conditions is neither implied nor guaranteed. electrical characteristics - input/supply/common parameters ta = t com or t ind ; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes t com commmercial range 0 70 c 1 t in d industrial range -40 85 c 1 input high voltage v ih single-ended inputs, except smbus, low threshold and tri-level inputs 2v dd + 0.3 v 1 input low voltage v il single-ended inputs, except smbus, low threshold and tri-level inputs gnd - 0.3 0.8 v 1 i in single-ended inputs, v in = gnd, v in = vdd -5 5 ua 1 i inp single-ended inputs v in = 0 v; inputs with internal pull-up resistors v in = vdd; inputs with internal pull-down resistors -200 200 ua 1 f ib yp v d d = 3.3 v, bypass mode 10 110 mhz 2 f i p ll v d d = 3.3 v, 100mhz pll mode 33 100.00 110 mhz 2 pin inductance l p in 7nh1 c in logic inputs, except dif_in 1.5 5 pf 1 c indif_in dif_in differential clock inputs 1.5 2.7 pf 1,4 c out output pin capacitance 6 pf 1 clk stabilization t stab from v dd power-up and after input clock stabilization or de-assertion of pd# to 1st clock 1.8 ms 1,2 input ss modulation frequency f modi n allowable frequency (triangular modulation) 30 33 khz 1 oe# latency t latoe# dif start after oe# assertion dif stop after oe# deassertion 1 3 cycles 1,3 tdrive_pd# t drvpd dif output enable after pd# de-assertion 300 us 1,3 tfall t f fall time of control inputs 5 ns 1,2 trise t r rise time of control inputs 5 ns 1,2 smbus input low voltage v ilsmb 0.8 v 1 smbus input high voltage v ihsmb 2.1 v ddsmb v1 smbus output low voltage v olsmb @ i pullup 0.4 v 1 smbus sink current i pullup @ v ol 4ma1 nominal bus voltage v ddsmb 3v to 5v +/- 10% 2.7 5.5 v 1 sclk/sdata rise time t rsmb (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata fall time t fsmb (min vih + 0.15) to (max vil - 0.15) 300 ns 1 smbus operating frequency f maxsmb maximum smbus operating frequency 100 khz 1,5 1 guaranteed by design and characterization, not 100% tested in production. 2 control input must be monotonic from 20% to 80% of input swin g . 5 the differential in p ut clock must be runnin g for the smbus to be active ambient operating temperature input current 3 time from deassertion until out p uts are >200 mv 4 dif_in input capacitance input frequency
idt ? two output differential buffer for pcie gen3 1667c?04/20/11 9db233 two output differential buffer for pcie gen3 5 datasheet electrical characteristics - clock input parameters ta = t com or t ind; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes input high voltage - dif_in v ihdif differential inputs (sin g le-ended measurement) 600 800 1150 mv 1 input low voltage - dif_in v ildif differential inputs (sin g le-ended measurement) v ss - 300 0 300 mv 1 input common mode volta g e - dif_in v com common mode input voltage 300 1000 mv 1 input amplitude - dif_in v swing peak to peak value 300 1450 mv 1 input slew rate - dif_in dv/dt measured differentiall y 0.4 8 v/ns 1,2 input leakage current i in v in = v dd , v in = gnd -5 5 ua 1 input duty cycle d tin measurement from differential wavefrom 45 55 % 1 input jitter - cycle to cycle j difin differential measurement 0 125 ps 1 1 guaranteed b y desi g n and characterization, not 100% tested in production. 2 slew rate measured through +/-75mv window centered around differential zero electrical characteristics - dif 0.7v current mode differential outputs t a = t com or t ind; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes slew rate trf sco p e avera g in g on 0.6 2.5 4 v/ns 1, 2, 3 slew rate matchin g trf slew rate matchin g , sco p e avera g in g on 9.5 20 % 1, 2, 4 voltage high vhigh 660 740 850 1 voltage low vlow -150 8 150 1 max volta g e vmax 760 1150 1 min volta g evmin -300-3 1 vswin g vswin g sco p e avera g in g off 300 1506 mv 1, 2 crossin g volta g e ( abs ) vcross_abs sco p e avera g in g off 250 378 550 mv 1, 5 crossing voltage (var) -vcross scope averaging off 54 140 mv 1, 6 2 measured from differential waveform 6 the total variation of all vcross measurements in any particular system. note that this is a subset of v_cross_min/max (v_cros s absolute) allowed. the intent is to limit vcross induced modulation b y settin g v_cross_delta to be smaller than v_cross absolute. mv statistical measurement on single-ended signal using oscilloscope math function. (scope averaging on) measurement on single ended signal using absolute value. (scope averaging off) mv 1 guaranteed by design and characterization, not 100% tested in production. iref = vdd/(3xr r ). for r r = 475 ? (1%), i ref = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50 ? (100 differential impedance). 3 slew rate is measured through the vswing voltage range centered around differential 0v. this results in a +/-150mv window arou nd differential 0v. 4 matching applies to rising edge rate for clock and falling edge rate for clock#. it is measured using a +/-75mv window centered on the average cross point where clock rising meets clock# falling. the median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 5 vcross is defined as voltage where clock = clock# measured on a component test board and only applies to the differential risi ng edge (i.e. clock rising and clock# falling). electrical characteristics - current consumption ta = t com or t ind ; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes operating supply current i dd3.3op all outputs active @100mhz, c l = full load; 70 80 ma 1 i dd3.3pd all diff pairs driven n/a ma 1 i dd3.3pdz all differential pairs tri-stated n/a ma 1 1 guaranteed by design and characterization, not 100% tested in production. powerdown current
idt ? two output differential buffer for pcie gen3 1667c?04/20/11 9db233 two output differential buffer for pcie gen3 6 datasheet electrical characteristics - output duty cycle, jitter, skew and pll characterisitics ta = t com or t ind; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes -3db point in high bw mode 2 2.3 4 mhz 1 -3db point in low bw mode 0.4 0.5 1 mhz 1 pll jitter peaking t jpeak peak pass band gain 1 2 db 1 duty cycle t dc measured differentially, pll mode 45 48 55 % 1 duty cycle distortion t dcd measured differentially, bypass mode @100mhz -2 1 2 % 1,4 t p dbyp bypass mode, v t = 50% 2500 3660 4500 ps 1 t p dpll hi bw pll mode v t = 50% -250 0 250 ps 1 skew, output to output t sk3 v t = 50% 15 50 ps 1 pll mode 40 50 ps 1,3 additive jitter in bypass mode 10 50 ps 1,3 1 guaranteed by design and characterization, not 100% tested in production. 2 i ref = v d d /(3xr r ). for r r = 475 ? (1%), i ref = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50 ? . 3 measured from differential waveform 4 duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in by pass mode. skew, input to output jitter, cycle to cycle t jcyc-cyc pll bandwidth bw electrical characteristics - pcie phase jitter parameters ta = t com or t ind; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes t jp hpcieg1 pcie gen 1 32 86 ps (p-p) 1,2,3 pcie gen 2 lo band 10khz < f < 1.5mhz 1.1 3 ps (rms) 1,2 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 2.3 3.1 ps (rms) 1,2 t jphpcieg3 pcie gen 3 (pll bw of 2-4mhz, cdr = 10mhz) 0.5 1 ps (rms) 1,2,4 t jphpcieg1 pcie gen 1 2 5 ps (p-p) 1,2,3 pcie gen 2 lo band 10khz < f < 1.5mhz 0.2 0.3 ps (rms) 1,2 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 0.8 1 ps (rms) 1,2 t jphpcieg3 pcie gen 3 (pll bw of 2-4mhz, cdr = 10mhz) 0.1 0.2 ps (rms) 1,2,4 1 applies to all outputs. 3 sam p le size of at least 100k c y cles. this fi g ures extra p olates to 108 p s p k- p k @ 1m c y cles for a ber of 1-12. 4 sub j ect to final radification b y pci sig. t jphpcieg2 2 see htt p ://www. p cisi g .com for com p lete s p ecs t jphpcieg2 phase jitter, pll mode additive phase jitter, bypass mode
idt ? two output differential buffer for pcie gen3 1667c?04/20/11 9db233 two output differential buffer for pcie gen3 7 datasheet common recommendations for differential routing dimension or value unit figure l1 length, route as non-coupled 50ohm trace 0.5 max inch 1 l2 length, route as non-coupled 50ohm trace 0.2 max inch 1 l3 length, route as non-coupled 50ohm trace 0.2 max inch 1 rs 33 ohm 1 rt 49.9 ohm 1 down device differential routing l4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max inch 1 l4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch 1 differential routing to pci express connector l4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max inch 2 l4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch 2 src reference clock hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express down device ref_clk input figure 1: down device routing hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express add-in board ref_clk input figure 2: pci express connector routing
idt ? two output differential buffer for pcie gen3 1667c?04/20/11 9db233 two output differential buffer for pcie gen3 8 datasheet vdiff vp-p vcm r1 r2 r3 r4 note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ics874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 standard lvds r1a = r1b = r1 r2a = r2b = r2 alternative termination for lvds and other common differential signals (figure 3) hcsl output buffer l1 l1' r1b l2 l2' r1a l4' l4 l3 r2a r2b down device ref_clk input figure 3 l3' r3 r4 component value note r5a, r5b 8.2k 5% r6a, r6b 1k 5% cc 0.1 f vcm 0.350 volts cable connected ac coupled application (figure 4) pcie device ref_clk input figure 4 r5a l4' l4 3.3 volts r5b r6a r6b cc cc
idt ? two output differential buffer for pcie gen3 1667c?04/20/11 9db233 two output differential buffer for pcie gen3 9 datasheet general smbus serial interface information for the ics9db233 how to write: ? controller (host) sends a start bit. ? controller (host) sends the write address d4 (h) ? ics clock will acknowledge ? controller (host) sends the begining byte location = n ? ics clock will acknowledge ? controller (host) sends the data byte count = x ? ics clock will acknowledge ? controller (host) starts sending byte n through byte n + x -1 (see note 2) ? ics clock will acknowledge each byte one at a time ? controller (host) sends a stop bit how to read: ? controller (host) will send start bit. ? controller (host) sends the write address d4 (h) ? ics clock will acknowledge ? controller (host) sends the begining byte location = n ? ics clock will acknowledge ? controller (host) will send a separate start bit. ? controller (host) sends the read address d5 (h) ? ics clock will acknowledge ? ics clock will send the data byte count = x ? ics clock sends byte n + x -1 ? ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . ? controller (host) will need to acknowledge each byte ? controllor (host) will send a not acknowledge bit ? controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p byte n + x - 1 data byte count = x beginning byte n stop bit x byte index block write operation slave address d4 (h) beginning byte = n write start bit controller (host) t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit ics (slave/receiver) controller (host) x byte ack ack data byte count = x ack slave address d3 (h) index block read operation slave address d4 (h) beginning byte = n ack ack
idt ? two output differential buffer for pcie gen3 1667c?04/20/11 9db233 two output differential buffer for pcie gen3 10 datasheet smbus table: device control register, read/write address (d4/d5) pin # name control function type 0 1 default bit 7 sw_en enables smbus control of bite 1 and 0 rw pll funct ions controlled by smbus re g isters pll funct ions controlled by device pins 1 bit 6 rw x bit 5 rw x bit 4 rw x bit 3 rw x bit 2 rw x bit 1 pll bw #adjust selects pll bandwidth rw low bw high bw 1 bit 0 pll enable bypasses pll for board test rw pll bypassed (fan out mode) pll enabled (zdb mode) 1 smb us table: output enable register pin # name control function type 0 1 default bit 7 rw x bit 6 rw x bit 5 rw x bit 4 rw x bit 3 rw x bit 2 rw x bit 1 rw x bit 0 rw x smbus table: function select re g ister pin # name control function type 0 1 default bit 7 rw x bit 6 rw x bit 5 rw x bit 4 rw x bit 3 rw x bit 2 rw x bit 1 rw x bit 0 rw x smbus table: vendor & revision id register pin # name control function type 0 1 default bit 7 rid3 r - - 0 bit 6 rid2 r - - 0 bit 5 rid1 r - - 0 bit 4 rid0 r - - 1 bit 3 vid 3 r - - 0 bit 2 vid 2 r - - 0 bit 1 vid 1 r - - 0 bit 0 vid 0 r - - 1 - reserved - - reserved - reserved - reserved - - reserved - - reserved - reserved reserved reserved - reserved - reserved - reserved reserved - - reserved - reserved - byte 0 - - reserved - reserved - - reserved - - reserved - - - byte 1 - - - - - - - - - - byte 2 - - - - byte 3 - revision id - - - vendor id - - - - reserved - reserved -
idt ? two output differential buffer for pcie gen3 1667c?04/20/11 9db233 two output differential buffer for pcie gen3 11 datasheet smbus table: device id pin # name control function t yp e0 1default bit 7 r 0 bit 6 r 0 bit 5 r 0 bit 4 r 0 bit 3 r 0 bit 2 r 1 bit 1 r 1 bit 0 r 0 smbus table: byte count register pin # name control function type 0 1 default bit 7 bc7 rw - - 0 bit 6 bc6 rw - - 0 bit 5 bc5 r w --0 bit 4 bc4 rw - - 0 bit 3 bc3 rw - - 0 bit 2 bc2 rw - - 1 bit 1 bc1 r w --1 bit 0 bc0 rw - - 0 - - - - byte 5 - writing to this register will configure how many bytes will be read back, default is 06 = 6 bytes. - - - - - - - b y te 4 - - - - - - - - - - device id = 06 hex - -
idt ? two output differential buffer for pcie gen3 1667c?04/20/11 9db233 two output differential buffer for pcie gen3 12 datasheet min max min max a 1.35 1.75 .053 .069 a1 0.10 0.25 .004 .010 a2 -- 1.50 -- .059 b 0.20 0.30 .008 .012 c 0.18 0.25 .007 .010 d e 5.80 6.20 .228 .244 e1 3.80 4.00 .150 .157 e l 0.40 1.27 .016 .050 n a 0808 zd in millimeters in inches common dimensions see variations 0.635 basic 0.025 basic common dimensions 20-lead, 150 mil ssop ( qsop ) see variations see variations see variations see variations symbol see variations 20-pin ssop package drawing and dimensions
idt ? two output differential buffer for pcie gen3 1667c?04/20/11 9db233 two output differential buffer for pcie gen3 13 datasheet min max min max a--1.20--.047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.19 0.30 .007 .012 c 0.09 0.20 .0035 .008 d e e1 4.30 4.50 .169 .177 e l 0.45 0.75 .018 .030 n a 0808 aaa -- 0.10 -- .004 variations min max min max 20 6.40 6.60 .252 .260 10-0035 see variations see variations 0.65 basic reference doc.: jedec publication 95, mo-153 n see variations see variations d mm. d (inch) 20-lead, 4.40 mm. body, 0.65 mm. pitch tssop 6.40 basic 0.252 basic 0.0256 basic common dimensions in millimeters in inches common dimensions (173 mil) (25.6 mil) symbol index area index area 12 1 n d e1 e sea ting plane sea ting plane a1 a a2 e -c- -c- b c l aaa c 20-pin tssop package drawing and dimensions ordering information part / order number shipping packaging package temperature 9db233aflf tubes 20-pin ssop 0 to +70c 9db233aflft tape and reel 20-pin ssop 0 to +70c 9db233afilf tubes 20-pin ssop -40 to +85c 9db233afilft tape and reel 20-pin ssop -40 to +85c 9db233aglf tubes 20-pin tssop 0 to +70c 9db233aglft tape and reel 20-pin tssop 0 to +70c 9db233agilf tubes 20-pin tssop -40 to +85c 9DB233AGILFT tape and reel 20-pin tssop -40 to +85c "lf" after the package code are the pb-free configuration and are rohs compliant. "a" is the device revision designator (will not correlate to the datasheet revision).
9db233 two output differential buffer for pcie gen3 14 datasheet innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support 408-284-6578 pcclockhelp@idt.com corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan idt singapore pte. ltd. 1 kallang sector #07-01/06 kolamayer industrial park singapore 349276 phone: 65-6-744-3356 fax: 65-6-744-1764 europe idt europe limited 321 kingston road leatherhead, surrey kt22 7tu england phone: 44-1372-363339 fax: 44-1372-378851 ? 2010 integrated device technology , inc. all rights reserved. product specifications subject to change without notice. idt, ic s, and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa revision histor y rev. who issue date description page # 0.1 r dw 4/28/2010 1. initial release 0.2 r dw 6/3/2010 1. updated pin names to mat ch other 9db devices clkreq# becomes oe# and pciexyy becomes dif_yy 2. updated maximum rise/fall time to 550ps from 700ps. this translates to a minimum slew rate of 0.67v/ns thus meeting the pci e spec of 0. 6v/ns. 3. updated phase jitter tables t o remove references to qpi. 4. reformatted ds t o have common format amongst all 9dbx33 ds. 5. updated block diagram to match item 1 6 0.3 r dw 6/25/2010 1. updated electrical tables to new standard format for 9db devices. 2. cleaned up front page text. 1, 3-6 a r dw 6/30/2010 released to final b r dw 7/12/2010 1. changed pwd to default in smbus tables. 10,11 c r dw 4/20/2011 c hanged pull down indicator from '**' to ' v '.

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